Mesochronous clock signals are often used to time signaling operations in synchronous memory systems. By using the same clock source to provide transmit/receive timing within both the memory controller and memory devices, frequency drift is avoided, resulting in a relatively simple, robust timing arrangement. Because the clock reference is distributed in space between controller and memory, however, the clock domains of the two chips generally have an arbitrary phase offset with respect to each other that must be compensated to enable synchronous communication. Complicating matters, the chip-to-chip phase offset tends to drift substantially with temperature and voltage, in large part due to the clock buffering circuitry provided within each chip to fan-out the clock to the various transmit and receive circuits.
Many modern memory systems manage the chip-to-chip phase drift by transmitting strobes or other source-synchronous timing signals to control data sampling within the recipient device, in effect extending the clock domain of the transmitting device into the receiving device. Unfortunately, this approach suffers a considerable power/cost penalty as additional signal drivers, pins and precisely routed signal lines (to match the propagation time between strobe and data lines) are usually required.
Another approach is to compensate for the drifting phase offset by providing a phase-locked loop (PLL) or delay-locked loop (DLL) within the memory controller and each memory device to maintain alignment between the reference clock and the distributed clock (i.e., the multiplicity of nominally same-phase clocks distributed to the various receive and transmit circuits). By this arrangement, a substantially fixed phase relationship may be maintained between the chips despite environmentally induced drift between their respective clock-buffer delays.
While the PLL/DLL approach avoids many of the penalties of source-synchronous arrangements (especially the consumption of precious pins), PLL and DLL circuits tend to be power hungry, consuming power even during idle periods (to maintain phase-lock) and requiring considerable time and additional power to restore phase-lock when awakened from a disabled, power-saving state. All these disadvantages are particularly problematic in mobile applications (e.g., cell phones, laptop computers and the like), where performance demands and bursty transaction profiles make it difficult to disable locked-loop operation and yet the large idle power of the locked-loop circuits drains precious battery life.